The microelectronics industry has consistently achieved ever shrinking device sizes and ever greater levels of device integration, resulting in higher interconnect densities. A steady succession of interconnect developments and strategies has evolved in the packaging industry to meet the demand of these high interconnect densities. Nearly all have been aimed at one goal, that is, reduced size. Reduced size almost always translates into lower cost. Thus in state of the art packaging, dual-in-line packages have been largely replaced by surface mount packages to meet the high density interconnect demand. These and similar developments are directed toward reducing the package area, i.e. the x-y dimension of the package. Furthermore, in many applications, especially those requiring larger semiconductor chips, there has been a need to utilize thin semiconductor chips. These issues have been addressed by techniques for thinning the wafers from which chips are singulated. The thinning operation is performed on fully processed wafers by mounting the wafer, active side down, on a temporary carrier such as an adhesive tape and then grinding or polishing the backside of the wafer. A variety of techniques have been proposed and used, ranging from simple mechanical abrasion using, e.g., an abrasive grinding wheel, to chemical etching and polishing techniques, and combinations of these, e.g. chemical-mechanical polishing.
In a typical wafer thinning process, a 200 millimeter (mm) diameter wafer of completed integrated circuits (ICs) may be reduced from an initial thickness of about 26 to about 30 thousandths of an inch (mils) to a final thickness of only about 10-12 mils before it is remounted and diced into IC chips or die. The individual IC chips or die are then packaged, which may involve assembly into an single chip module (SCM) or multi-chip module (MCM). The term module as used herein refers to a sub-assembly of at least two components, a substrate, and at least one active chip which is flip chip bonded to the substrate.
Solder bump or solder ball interconnections are typically formed on a wafer from which flip chips are formed before thinning and dicing is performed. Thinning a solder bumped wafer presents many handling issues associated with securing the bumped wafer during the thinning process. In the subsequent process of making thinned flip chips, many process and handling steps, for example the dicing step, are performed on the bumped thinned wafer. To withstand the thinning process itself and subsequent process and handling without damage or fracture, wafer thinning can be performed to a thickness of about 10 mils or greater. A final flip chip thickness of less than about 10 mils, which would otherwise be desirable for many applications, is prohibited by the bumped wafer thinning process itself and exposure to the subsequent process and handling steps. This limitation, about 10 mils or greater, is generally accepted in the industry as a norm. This constraint rules out the use of thin flip chips (flip chips having a thickness of less than about 10 mils) in several important applications.
A technique for assembling a flip chip to a substrate to make an electronic package without the solder bumps or solder balls interconnections being a part of the flip chip, would enable flip chips to be used that are thinned to less than about 10 mils thick, and would be a substantial advance in packaging technology.